/*	DE_MORGAN_1_TEST	*/
`timescale	1ns/1ns
//`include "MORGAN1.V"
module	DE_MORGAN_1_TEST;
reg	A, B;
wire	OUT_LHS, OUT_RHS;
	DE_MORGAN_1	DE_MORGAN_1	( A, B, OUT_LHS, OUT_RHS );
	initial	begin
　　　$dumpfile("morgan1.vcd");
      $dumpvars(0, DE_MORGAN_1_TEST);
			A = 0;	B = 0;
		#100	A = 1;
		#100	A = 0;	B = 1;
		#100	A = 1;
		#100	$finish;
	end
endmodule