`timescale 1ns/1ns

module counter_top;
     reg  clk, res;
       wire [2:0] q;

       parameter RATE = 100;
       always #(RATE/2) clk = ~clk;

       counter_oct counter_oct_i (.clk(clk), .res(res), .q(q));

       initial begin
          $dumpfile("test.vcd");
          $dumpvars(0, counter_top);

          #0  res = 0; clk = 0;
          #RATE res = 1; // initilaize
          #RATE res = 0;
          #(RATE*8)
            $finish;
       end
       initial $monitor ($stime, " res=%b clk=%b q=%o", res, clk, q);
endmodule